Process Development for and Fabrication of APSM Set and Overlay Metrology Wafers

SOL #: NB305000-26-00527Special NoticeSole Source

Overview

Buyer

Commerce
National Institute Of Standards And Technology

Place of Performance

Gaithersburg, MD

NAICS

Semiconductor and Related Device Manufacturing (334413)

PSC

No PSC code specified

Set Aside

No set aside specified

Timeline

1
Posted
Apr 30, 2026
2
Action Date
May 14, 2026, 4:00 PM

Qualification Details

Fit reasons
  • NAICS alignment with historical contract wins in similar service areas.
  • Scope strongly matches core technical capabilities and delivery model.
Risks
  • Past performance thresholds may require one additional teaming partner.
  • Potential clarification needed on staffing minimums before bid/no-bid.
Next steps

Validate eligibility requirements, assign capture owner, and schedule partner outreach to confirm teaming strategy before submission planning.

Quick Summary

The National Institute of Standards and Technology (NIST), under the Department of Commerce, has issued a Special Notice combining a sources sought and an intent to sole source for Process Development for and Fabrication of APSM Set and Overlay Metrology Wafers. This notice seeks to identify potential sources for specialized wafers and mask sets required for NIST's CHIPS R&D Program, specifically for SEM-based overlay metrology research. If no other capable sources are identified, NIST intends to award a sole source contract to AMAG CONSULTING, LLC. Responses are due May 14, 2026.

Scope of Work

NIST requires the process development and fabrication of:

  • Attenuated Phase Shift Mask (APSM) Set: A minimum of two masks suitable for fabricating overlay metrology wafers. These masks must include various overlay patterns (box-in-box, image-based, advanced imaging metrology, Hitachi-type SEM-based) with varying sizes (less than 150 mm to smaller than 50 mm range) and intentional offsets (1, 2, 5, 10 nm). Masks must be protected and include GDSII-based maps and documentation.
  • Overlay Metrology Wafers: A minimum of four 300 mm Si wafers patterned with the same specified overlay patterns and offsets. Wafers must be delivered in clean-room-compatible enclosures, with GDSII-based maps and documentation on properties, materials, and the patterning process.

These items are crucial for developing imaging and measurement solutions for integrated circuit (IC) overlay metrology using scanning electron microscopes, supporting the CHIPS Act activities.

Contract & Timeline

  • Type: Special Notice (Sources Sought / Intent to Sole Source)
  • NAICS: 334413, Semiconductor and Related Device Manufacturing (Small Business Size Standard: 1,250 employees)
  • Set-Aside: None specified (market research stage, intent to sole source)
  • Response Due: May 14, 2026, 12:00 PM EST
  • Questions Due: May 5, 2026, 11:00 AM EST
  • Published: April 30, 2026
  • Place of Performance: Gaithersburg, MD

Response Instructions

Interested parties must submit a written capability statement via email to Sadaf.Afkhami@nist.gov. The statement should include:

  • Company name, address, UEI, CAGE code, and point-of-contact.
  • Business size and socio-economic status for NAICS 334413.
  • Description of relevant capabilities and prior experience.
  • Identification of applicable contract vehicles.
  • Manufacturing location (US or foreign). Submissions are limited to 12 pages, Times New Roman 11pt.

Additional Notes

This notice is for market research purposes. NIST conducted prior market research and identified AMAG CONSULTING, LLC as the only vendor capable of meeting requirements due to their unique ability to create attenuated phase shift masks. If other capable vendors are identified through this notice, NIST will review the information to determine appropriate solicitation methods. This is not a Request for Proposal and does not guarantee a contract award.

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Special Notice
Posted: Apr 30, 2026
Process Development for and Fabrication of APSM Set and Overlay Metrology Wafers | GovScope