TECHNOLOGY/BUSINESS OPPORTUNITY Noble-Ice-Modulated Superconducting Circuit
Overview
Buyer
Place of Performance
NAICS
PSC
Set Aside
Original Source
Timeline
Qualification Details
Fit reasons
- NAICS alignment with historical contract wins in similar service areas.
- Scope strongly matches core technical capabilities and delivery model.
Risks
- Past performance thresholds may require one additional teaming partner.
- Potential clarification needed on staffing minimums before bid/no-bid.
Next steps
Validate eligibility requirements, assign capture owner, and schedule partner outreach to confirm teaming strategy before submission planning.
Quick Summary
The Lawrence Livermore National Laboratory (LLNL), under the U.S. Department of Energy, is offering a Technology/Business Opportunity for collaboration to further develop and commercialize its noble-ice-modulated superconducting circuit. This is NOT a procurement. LLNL is seeking industry partners with demonstrated ability to bring this invention to market. Statements of interest are due by May 16, 2026.
Technology Overview
LLNL's innovation addresses critical limitations in superconducting resonators and qubits, which require precise frequency targeting but suffer from manufacturing variations and environmental factors. Existing tuning methods are often limited in range, introduce noise, drift, or add complexity/loss. The noble-ice-modulated superconducting circuit utilizes a neon-filled, hermetic package where a thin film of solid neon coats a superconducting-resonator chip at millikelvin temperatures. On-chip heaters briefly raise local spots to approximately 25 K, causing the neon ice to sublimate and redeposit, thereby thinning or thickening the ultra-low-loss dielectric. This process precisely shifts resonator or qubit frequencies (kHz precision over MHz-GHz range) in situ. After tuning, heaters deactivate, leaving a passive, loss-free device.
Advantages & Applications
This technology offers significant advantages over current methods, including kHz-level accuracy and MHz-to-GHz range, zero added loss, simplicity (using existing mask sets, no extra materials or bias wiring), and post-cooldown adjustability. These benefits translate to economic value through looser lithography specs, higher wafer yield, denser qubit/MKID packing, reduced costs, and improved gate fidelity/sensor resolution. Potential applications span the entire cryogenic-electronics landscape, including superconducting quantum processors (e.g., IBM, Google), commercial wafer foundries, Microwave Kinetic-Inductance Detector (MKID) arrays for telescopes, satellite IR imagers, and fundamental physics experiments (e.g., axion haloscopes). The current Technology Readiness Level (TRL) is 0-2, and LLNL has filed for patent protection.
Collaboration Details
LLNL is seeking industry partners to commercialize this technology. Interested companies must provide an electronic or written statement of interest including: company name and address, point of contact information (name, address, telephone), and a description of corporate expertise and/or facilities relevant to commercializing this technology. All licensing activities adhere to strict nondisclosure policies for company proprietary information.
Timeline & Contacts
- Opportunity Type: Special Notice (Technology/Business Opportunity)
- Response Due: May 16, 2026, 6:00 PM ET
- Published Date: April 16, 2026
- Agency: Department of Energy / LLNS – DOE CONTRACTOR
- Primary Contact: Clarence Cannon (cannon15@llnl.gov, 925-423-3989)
- Secondary Contact: Charlotte Eng (eng23@llnl.gov, 925-422-1905)
- Website: https://ipo.llnl.gov/resources for more information on working with LLNL.